The present invention generally relates to a process for improving capacitance extraction performance in a circuit, and more specifically, to a process for more efficiently estimating parasitic capacitance that may be present in the wiring paths in a VLSI (very large scale integrated) chip.
As VLSI chips have scaled over the decades, interconnect or wire width and spacing has also scaled. If not properly designed, this scaling can be a limiter of circuit performance. For example, unintended capacitive coupling between two wires that are next to each other can often occur. When this happens, one signal can capacitively couple with another and cause what appears to be noise. As such, it is crucial to accurately estimate parasitic capacitance that may be created by proposed wiring paths prior to actually manufacturing a circuit.
Notably, global interconnects will have very large numbers of nets and shapes making up the nets, which can strain memory. Conventional processes, such as that which is taught in U.S. Pat. No. 6,061,508, which is hereby incorporated by reference in its entirety, involve collecting the coordinates of at least one interconnect, identifying and classifying each metal layer within the region of the interconnect, identifying the edges of the interconnect, identifying neighboring interconnects in a direction perpendicular to each side of the original interconnect, and calculating the parasitic capacitance between the original interconnect and all neighboring interconnect shape edges.
However, one drawback to this type of process is time. Indeed, extraction of a large flat core can take many hours (>12). Accordingly, a system and method for more efficiently estimating parasitic capacitance without sacrificing accuracy would be beneficial.